1. Technical Field
The present invention generally relates to data processing systems, and in particular a method and system for identifying intra-chip events. More particularly, the present invention relates to tracking the occurrence of otherwise hidden events utilizing transaction interface logic and underutilized system interconnects.
2. Description of the Related Art
It is becoming increasingly difficult to diagnose failures in, and to measure the performance of, state-of-the-art data processing systems. This is because modem microprocessors not only operate at ever increasing clock speeds, but may also execute instructions in parallel, out of order, and speculatively. Moreover, visibility of a microprocessor's inner state has becoming limited due to the sheer design complexity and also due to practical limitations on the number of available external contact pins that may be provided on a chip package.
Conventional hardware diagnostic and performance measurement tools are typically external logic analyzers and in-circuit emulators. Logic analyzers are capable of monitoring signals on external pins and signals that are otherwise externally accessible. Logic analyzers are also capable of capturing the state of these signals and generating triggers in response to the captured signal states. However, since logic analyzers rely solely on externally available signals, they cannot analyze and/or trigger on signals that are entirely internal to a chip (i.e., signals that do not extend to pins of the chip). In-circuit emulators address this problem by mimicking the functionality of a microprocessor, thus providing visibility to the microprocessor's internal state and signals. However, since an in-circuit emulator only emulates a microprocessor's functionality, it cannot provide an absolutely accurate representation of a silicon embodiment of a microprocessor. As a result, in-circuit emulators are more useful for debugging system software than system hardware. Furthermore, simulation of complex on-chip systems, such as multiprocessor designs, by in-circuit emulators is impracticable in terms of cost and complexity.
One approach that partially addresses the foregoing limitations is to implement an on-chip debugging system. One such system is disclosed in U.S. Pat. No. 5,951,696, titled “Debug System With Hardware Breakpoint Trap”, issued Sep. 14, 1999 to Naaseh, et al. An on-chip system for debugging a microprocessor is disclosed therein that provides visibility of a chip's internal state without interfering with the normal state of the object silicon device (i.e., test and debug occur under actual system environment conditions, and while the microprocessor is operating “at speed”). The central feature of the technique employed by Naaseh et al. is utilization of a hardware breakpoint trap (HBT) that is triggered in response to a programmed combination of a number of triggers to allow the current state of the processor to be preserved prior to, and restored following, capture of a debug event. The HBT generation means (i.e., trigger and event generation means) are incorporated within the microprocessor chip, while requisite debug software utilized for preserving and restoring a current processor state is stored anywhere in the system's memory.
The system set forth by Naaseh et al. utilizes dedicated debug busses for carrying the debugging data off the chip to external debug equipment. Although the implementation of on-chip debugging functionality reduces the number of external pins required as circuit access points for logic analyzers and the like, at least some additional pins are required to accommodate the dedicated debug busses. Another problem with the dedicated debug bus disclosed by Naaseh et al. is that it does not provide a means by which captured debug can be selectively routed and thus conveniently accessed and processed within a given data processing system.
The need for an improved pervasive debugging tool is becoming particularly great with the continued development of complex data processing systems contained within one or only a few discrete silicon elements. Examples of situations requiring a comprehensive debug system include system-on-chip technology, and hierarchical data storage systems shared by multiple processors.
From the foregoing, it can therefore be appreciated that a need exists for an improved debugging tool that provides an accurate in-circuit representation of diagnostic signals without the need for additional pins to route such signals to off-chip equipment.